1. Field of the Invention
This invention relates generally to the field of semiconductor memory devices and, more particularly, to a message box memory cell for two-side asynchronous access.
2. Description of the Related Art
Sometimes, two devices wish to communicate with each other. These devices may be individual processors or a processor system having two or more processor cores. Typically, the devices are operating at different rates and thus, work asynchronously with respect to each other. One known technique for allowing data interchange is to provide a message box between the asynchronous devices.
The message box can be a multi-port SRAM (static random access memory) or a register created out of multiple SRAM cells. A typical SRAM array is illustrated in FIG. 1. The SRAM consists of a matrix of storage bits with bit capacity 2.sup.N .times.2.sup.M bits arranged in an array 200 with 2.sup.M columns (bit lines) and 2.sup.N rows (word lines). To read data stored in the array 200, a row address is input and decoded by row decoder 202 to select one of the rows or word lines. All of the cells along this word line are activated. A column decoder 204 then addresses one bit out of the 2.sup.M bits that have been activated and routes the data that is stored in that bit to a sense amplifier (not shown) and then out of the array 200. Data in and Data out are controlled by the Read/Write Control circuit 206.
A conventional SRAM cell consists of a basic bistable flip-flop circuit which needs only a DC current applied to retain its memory. A conventional SRAM cell 10 is illustrated in FIG. 2. The cell 10 includes two inverters 14, 16 and two control transistors 18, 20. The output of the second inverter 16 is connected to the input of the first inverter 14 and a first node A. The output of the first inverter 14 is connected to the input of the second inverter 16 and a second node B. The two inverters 14, 16, as connected, define a flip-flop 12. The first transistor 18 is connected between the first node A and a first bit line BL. The second transistor 20 is connected between the second node B and a second bit line BLN. A word line WL is connected to the gate terminal of the two transistors 18, 20. Data is stored with either a high potential at node A and a low potential at node B, or a low potential at node A and a high potential at node B. This means that two stable states are available which are respectively defined as a logic 1 or a logic 0.
The logic state of the SRAM cell 10 is read by sensing the current on the bit line pair comprised of bit lines BL and BLN and/or the differential voltage developed thereon. When a word line VVL is selected, cell 10 is activated by turning on the two transistors 18, 20. If the activated SRAM cell 10 is in a logic 1 state, node A is high and node B is low. If the activated SRAM cell 10 is in a logic 0 state, node A is low and node B is high. Similarly, data is stored into the cell 10 by activating the WL and placing the appropriate current or differential voltage on the two bit lines BL, BLN. In the conventional SRAM cell 10, read and write operations are performed in an alternate manner since the cell 10 uses only one pair of bit lines BL, BLN. This is not suitable for a mailbox used for communications between asynchronous devices.
FIG. 3 illustrates a proposed multi-port 1write-1read (1W-1R) SRAM cell 30 to be used in a mailbox. The cell 30 includes two inverters 34, 36 and four control transistors 38, 40, 42, 44. The output of the second inverter 36 is connected to the input of the first inverter 34 and first and second nodes A1, A2. The output of the first inverter 34 is connected to the input of the second inverter 36 and third and fourth nodes B1, B2. The two inverters 34, 36, as connected, define a flip-flop 32.
The first transistor 38 is connected between the first node A1 and a first write bit line WBL. The second transistor 40 is connected between the third node B1 and a second write bit line WBLN. A write word line WWL is connected to the gate terminal of the first and second transistors 38, 40. The third transistor 42 is connected between the second node A2 and a first read bit line RBL. The fourth transistor 44 is connected between the fourth node B2 and a second read bit line RBLN. A read word line RWL is connected to the gate terminal of the third and fourth transistors 42, 44. Data is stored with either a high potential at nodes A1, A2 and a low potential at nodes B1, B2 or a low potential at nodes A1, A2 and a high potential at nodes B1, B2. This means that two stable states are available which are respectively defined as a logic 1 or a logic 0.
The SRAM cell 30 is designed such that there is one read port controlled by a read word line RWL and one write port controlled by a write word line WWL. The logic state of the SRAM cell 30 is read by sensing the current on the read bit line pair comprised of read bit lines RBL and RBLN and/or the differential voltage developed thereon. When a read word line RWL is selected, cell 30 is activated by turning on the transistors 42, 44. If the activated SRAM cell 30 is in a logic 1 state, node A2 is high and node B2 is low. If the activated SRAM cell 30 is in a logic 0 state, node A2 is low and node B2 is high. Similarly, data is stored into the cell 30 by activating the write word line WWL and placing the appropriate current or differential voltage on the two word bit lines WBL, WBLN. Although the SRAM cell 30 has individual read and write bit lines, the cell 30 is not suitable for a mailbox used for communications between asynchronous devices because simultaneous read and write operations could occur which would lead to corruption of the cells contents.
In addition, the cell 30 (and the cell 10 of FIG. 2) is subject to capacitive coupling between the bit lines when incorporated into a memory array. Capacitive coupling leads to coupling noise which could reverse the potential relationship between the differential bit lines. Any circuitry utilizing this cell 30 would have to compensate for the coupling noise. One know solution is to delay the operation of the sense amplifiers which slows down the operation memory. This is undesirable.
FIG. 4 illustrates a proposed multi-port 1write-2read (1W-2R) SRAM cell 60 to be used as a mailbox. The cell 60 contains the same configuration as the cell 30 illustrated in FIG. 2 except that two read ports are created by using read bit lines RBL1, RBL2 that are not differential. The SRAM cell 60 is designed such that there are two read ports respectively controlled by first and second read word lines RWL1, RWL2 and one write port controlled by a write word line WWL. Data is stored into the cell 60 in the same manner as described for cell 30 (FIG. 2).
It must be noted that two read ports are not differential and that the logic state of the SRAM cell 60 is directly read from each read bit line RBL1, RBL2. The read operation is dependent upon the pull-up/pull-down strength of the cell 60. When the first read word line RWL1 is selected, cell 60 is activated by turning on the third transistor 42. The contents of the cell 60 will be placed on the first read bit line RBL1. When the second read word line RWL2 is selected, cell 60 is activated by turning on the fourth transistor 44. The contents of the cell 60 will be placed on the second read bit line RBL2.
Although the SRAM cell 60 has individual read and write bit lines for one device and an individual read line for a second device, the cell 60 is not suitable for a mailbox used for communications between asynchronous devices because simultaneous read and write operations could occur which would lead to corruption of the cells contents. In addition, since the read bit lines are not differential, the operation of the cell 60 is very slow.
It is essential that any message box used between two or more devices to be able to handle a read and write operation that occurs at the same time without having its contents corrupted. This is of particular importance when the two devices are operating asynchronously. As stated above, none of the cells 10, 30, 60 are capable of handling simultaneous reads and writes. In addition, bit line coupling may occur at any time during a read cycle and the operation of one device may disturb the operation of the other device particularly when one device has activated the word lines and the other device initiates a read. Accordingly, there is a desire and need for a memory cell suitable for a message box between asynchronous devices that will not have its contents destructed by simultaneous read and write operations. In addition, there is a desire and need for a memory cell suitable for a message box between asynchronous devices capable of overcoming bit line coupling.